Implementation of the Sorting Schemes in a Programmable Logic

Experiments at the Large Hadron Collider (LHC) at CERN require a sophisticated multilevel trigger systems for data selection. At the Compact Muon Solenoid (CMS) experiment, the main task of Level 1 Trigger is to reduce the frequency of events from 40MHz down to 100kHz [1]. There are three major muon subsystems at the CMS: Cathode Strip Chambers (CSC), Drift Tubes (DT), and Resistive Plate Chambers (RPC). The Level 1 decision should be made about 3 μs after an interaction in the collision area, so only simple algorithms implemented in hardware can be used at this level. The current design requires that only the four best trigger candidates from each muon subsystem be passed to the Global Muon Trigger (GMT) System. It is considered that there is a sorter at the upper level of each muon subsystem trigger chain, which selects the four best candidates out of several tens of incoming and transmits them to the GMT. We propose a fast and flexible solution which would allow the implementation of such sorters for the various CMS muon subsystems. Four sorting schemes “3 objects out of 18”, “4 objects out of 8”, “4 objects out of 24” and “4 objects out of 36” are discussed. The first one is intended for the Muon Port Card [2] being designed for the CSC Trigger Electronics. The second scheme can be used for the RPC Sorting Processor [3]. The third scheme can be used for the DT Muon Sorter [4]. The fourth scheme is targeted to CSC Muon Sorter [2]. Designs based on Altera 20KE [5] Programmable Logic Devices (PLD) and results of simulation are presented. I. DESIGN ASSUMPTIONS We assume that sorting is based on the value of input patterns: higher ranks correspond to “better” patterns for the purpose of sorting. All schemes are targeted to a single chip implementation in order to reduce the overall sorting time. Each sorter chip receives 8, 18, 24 or 36 input patterns and outputs an addresses of three or four best patterns. The addresses of incoming patterns are assigned inside the sorter chip for the first, third and fourth schemes and obtained from the outer logic for the second scheme. If sorting objects contain more bits than the patterns that are used for the sorting, they should be temporarily pipelined in the external registers, and the addresses of the best patterns can be used for their further multiplexing onto outputs of the sorter board. This pipelining as well as a sorting logic can be done in a single chip if it has a sufficient number of input and output pins. We have implemented our sorting schemes for the 7and 8-bit patterns, which is typical for the CMS muon trigger systems. We assume that all patterns come to the sorter device in parallel being synchronized with its master clock. The input and output latches for all patterns and their addresses provide a reliable synchronous operation and predictable timing. All our designs are targeted to applications at the LHC experiments, where the main operating clock frequency is 40.08Mhz, so our goal was to achieve a registered performance of 40+ MHz for all sorting schemes with the minimal latency. Finally we assume that all inputs are not preselected (or ranked), but all the output patterns should be ranked, or present on the outputs of the sorter chip in descending order. II. TARGETED DEVICES AND DESIGN